VHDL Code for Comparator (4 bit)

Q. How do I write VHDL code for 4 bit Comparator

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp1 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
less : out STD_LOGIC;
equal : out STD_LOGIC;
greater : out STD_LOGIC);
end comp1;
architecture Behavioral of comp1 is
begin
process(A,B)
begin
if(A<B)then
less<='1';
equal<='0';
greater<='0';
elsif(A=B)then
less<='0';
equal<='1';
greater<='0';
else
less<='0';
equal<='0';
greater<='1';
end if;
end process;
end Behavioral;

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