VHDL Code For Decoder (2:4)

Q. How do I write VHDL code for Decoder (2:4)

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decod1 is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (3 downto 0));
end decod1;
architecture Behavioral of decod1 is
begin
process(I0,I1,En)
begin
if(En='1')
then
Y(0)<=(not I0) and (not I1);
Y(1)<=(not I0) and I1;
Y(2)<=I0 and (not I1);
Y(3)<=I0 and I1;
else
Y<="0000";
end if;
end process;
end Behavioral;

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