VHDL Code For Up-Down Counter

Q. How do I write VHDL code for Up-Down Counter

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ud is
Port ( clk,clr,up_down,sload : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end ud;
architecture Behavioral of ud is
signal tmp: STD_LOGIC_VECTOR(3 downto 0);
begin
process(clk,clr,sload)
begin
if(sload='1')then
if(clr='1')then
tmp<="0000";
elsif(clk'event and clk='1')then
if(up_down='1')then
tmp<=tmp + 1 ;
else
tmp<=tmp - 1;
end if;
end if;
end if;
end process;
Q<=tmp;
end Behavioral;

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