VHDL code for DEMUX(1:4)

Q. How do I write VHDL code for DE-Multiplexer

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux1 is
Port ( I : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (3 downto 0));
end demux1;
architecture Behavioral of demux1 is
begin
process(I,S0,S1)
begin
if(S1='0' and S0='0')then
Y<="0001";
elsif(S1='0' and S0='1')then
Y<="0010";
elsif(S1='1' and S0='0')then
Y<="0100";
elsif(S1='1' and S0='1')then
Y<="1000";
end if;
end process;
end Behavioral;

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