Q. How do I write VHDL code for Half-Subtractor
Ans:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hs1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; diff : out STD_LOGIC; borrow : out STD_LOGIC); end hs1; architecture Behavioral of hs1 is begin diff<=a xor b; borrow<=(not a) and b; end Behavioral;
If You Liked This Post Please Take a Time To Share This Post
vhdl program to subtract two 4-bit numbers and then square the result and then add the result. how to perform this program
ReplyDelete