VHDL code for Full-Adder

Q. How do I write VHDL code for Full Adder

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
sum : out STD_LOGIC);
end fa1;
architecture Behavioral of fa1 is
begin
sum<=a xor b xor cin;
cout<=(b and cin)or(a and b)or(a and cin);
end Behavioral;

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