VHDL Code For T Flip-Flop

Q. How do I write VHDL code for T Flip Flop

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( clk : in  STD_LOGIC;
reset : in  STD_LOGIC;
t : in  STD_LOGIC;
q : out  STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal q_reg: std_logic;
signal q_next: std_logic;
begin
process(clk)
begin
if (reset = '1') then
q_reg <= '0'; elsif (clk'event and clk = '1') then q_reg <= q_next;
end if;
end process;
q_next <= q_reg when t = '0' else not(q_reg);
q <= q_reg;
end Behavioral;  

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