VHDL Code For JK Flip-Flop

Q. How do I write VHDL code for JK flip-flop

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity J_K_flip_flop is
port(J,K,clock,reset: in bit; q: inout bit; qbar: out bit);
end J_K_flip_flop;
architecture synchronous_reset_J_K_flip_flop_behavioural of J_K_flip_flop is
begin
process(clock)
begin
if clock='0' and clock'event then 
if reset='1' then
q<='0';
else
q<=(((J and (not q)) or ((not K) and q));
end if;
end if;
end process;
qbar<=(not q);
end synchronous_reset_J_K_flip_flop_behavioural;

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