VHDL Code for Half-Adder

Q. How do I write VHDL code for Half Adder

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end ha1;
architecture Behavioral of ha1 is
begin
sum<= a xor b;
carry<=a and b;
end Behavioral;

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