VHDL Code for Encoder (4:2)

Q. How do I write VHDL code for Encoder

Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encod is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : out  STD_LOGIC_VECTOR (1 downto 0));
end encod;
architecture Behavioral of encod is
begin
process(a)
begin
if(a(0)='1')then
b<="00";
elsif(a(1)='1')then
b<="01";
elsif(a(2)='1')then
b<="10";
elsif(a(3)='1')then
b<="11";
end if;
end process;
end Behavioral;

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